Core: RISC-V RV32IM instruction supported, 3 stage pipeline (up to 200MHZ), 2 DMA and MPU (Memory Protection Unit)
Operation Conditions: Vcc3.3V, Vdd 1.2V
Memories：24KB instruction SRAM，separate into 3 banks;16 to 32KB data SRAM;Additional dual 0KB/9KB/16KB Memio SRAM can be used as data SRAM for adaptive
0，9x8 or 16x12 Rocells on different chip serials.
Each Rocell has at least 15 operations
Many Rocells has 32 bits integer multiplier and single precision FPU.
Reprogrammable Bus matrix to connect from Memio to Rocell Array
Single line of Memio is 256x32bits
Up to 80 reconfigurable GPIOs
Group based IO Remap, each group has 8 pins.
Debug mode: JTAG Interfaces (GPA)
Programming Interface: SPI (GPG)
Dual 8 channel DMA controller
Four 16-bit timers,
One 32-bit timer,
Air Condition, Refrigerator, Dish Washer, etc.
Robot, Toys, Motor Control, etc.
Electrical Bicycle, Balancing car, etc.
MCU + DSP
MCU + Low End FPGA
MCU+DSP+ Low End FPGA
Qingdao, Shandong, China
Qingdao Robei Electronics LTD.
Room 1005, Bld. A, Kaifon International Building, High-Tech Area, Qingdao, Shandong Province, China 266109
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