Core: RISC-V RV32IM instruction supported, 3 stage pipeline (up to 200MHZ), 2 DMA and MPU (Memory Protection Unit)
Operation Conditions: Vcc3.3V, Vdd 1.2V
Memories：24KB instruction SRAM，separate into 3 banks;16 to 32KB data SRAM;Additional dual 0KB/9KB/16KB Memio SRAM can be used as data SRAM for adaptive
0，9x8 or 16x12 Rocells on different chip serials.
Each Rocell has at least 15 operations
Many Rocells has 32 bits integer multiplier and single precision FPU.
Reprogrammable Bus matrix to connect from Memio to Rocell Array
Single line ...
Chenxi Adaptive Datasheet
RAC101xx is pure MCU which can support RV32IM Instructions, with 2 QSPIs, 2 UARTs,three 16 bits Timers and one 32 bits Timer, etc.
RAC102xx contains RAC101xx plus 9x8 Adaptive array.
RAC102xx contains RAC101xx plus 16x12 Adaptive array....
On August 26th, 2015, Robei held Adaptive Chip Press conference. President of Robei: Guosheng Wu explained the detail concept of Adaptive Chip. In the afternoon, the internship students in Robei displayed their summer research achivements. Many Chinese news and industrial website reported this conference.