Robei

Robei 简介 | Who we are?

若贝(Robei)是由美国硅谷的工程师创建的新型集成电路公司,拥有自主知识产权的若贝平行芯片和Robei芯片设计软件。公司于2012年在美国内华达州拉斯维加斯市注册,成功研发Robei芯片设计软件,一种全新的面向对象的可视化芯片设计软件。2014年初,若贝在青岛高新区设立了研发中心,专注于平行芯片的研发。

 

Robei Founded in Henderson, NV, USA by many electrical engineers in Silicon Valley, Califonia which provides visual chip design software(Verilog) released in 2012, and parallel design software coming soon with Robei parallel chip. Start from Jan. 2014, Robei set up research center in Qingdao, Shandong Province, China. Our office beyong the lake with a nice view of High-Tech Zone.

 

Robei 产品 | What we make?

1. Robei 平行芯片 | Robei Parallel Chip

若贝第一代平行芯片具备256个Rocell异构计算核心,其中64个带有IEEE-754标准的浮点计算单元,64个带有缓存FIFO和查找表。256异构核心可以同时运行,相互衔接。平行芯片兼顾了FPGA的并行计算能力,也通过32位的计算核心降低了设计复杂度,兼顾Risc计算指令,准确控制时序。IP单核运行频率可达最低500MHZ,内部带宽可超越1024bit。芯片运行频率为0-200MHZ。 自适应芯片可以应用在图像处理、雷达数据处理、无人机、AR、VR、卫星、机器人、大数据、智,智能能摄像头、手机、平板、电视机、投影仪等领域。重构一次操作时间可控制在微秒级别,最小可到纳秒级别。若贝平行芯片可以独立出售,也可以以硬核IP授权的形式与各大厂商合作。授权核心数可以涵盖64核、256核、1024核、4096核和16384核。平行芯片配置软件可以运行在各种主流操作系统和嵌入式操作系统(Android),界面式配置方式即使是高中生都能操作自如。平行芯片具备损坏避开功能,可以提升卫星使用寿命。同时,该能力让平行芯片具备协助工艺厂商实现逻辑缺陷检测,提升良率的作用。已经有很多12英寸厂商前来洽谈合作。

点此下载Robei 256核芯片PDF 版本的Datasheet

Robei Parallel chip has heterogeneous 256 Rocell computational cores with 64 IEEE-754 float point units and 64 fifo and look up tables. Robei chip has parallel processing functions like FPGA, but program like Risc computers. Robei Parallel chip IP can operate at maximum 500MHZ for each core, internal bandwidth can reach over 1024 bit. But because GPIO speed limit, this chip can only operate at 0-200MHZ with USB 3.0 interface with controllers. The applications include image processing, radar data processing,umaned vichecles, AR, VR, satellite hardware remote updating, robotics, big data, intelligent camera, cellphone, tablet, TV, projectors. Robei parallel chip can be dynamic reconfigured in nano-second to micro-second. Our company provides chip level solutions as well as IP integration service with 64 cores, 256 cores, 1024 cores, 2048 cores and 16384 cores choices. The configration software can run on Linux, Windows, Android with little requirements for hardware knowledge. Parallel chip avoids broken cores, which can help satellite to increase lifetime,as well as silicon fabs to detect logic detection. Currently, we already have many intensions from different fabs.

Click here to download Robei 256 cores datasheet in PDF format

 

2. Robei芯片设计软件 | Robei Visual Chip Software

Robei是一款可视化的跨平台EDA设计工具,提供了超级简化的设计流程,最新可视化的分层设计理念,透明的模型库和非常友好的用户界面。Robei软件将芯片设计高度抽象化,并精简到三个基本元素,掌握这三个基本元素,就能很快地掌握Robei的使用技巧。该软件将先进的图形化与代码设计相融合,让框图与代码设计优势互补,弱势相互抵消。Robei软件是世界上最小的芯片设计仿真工具,也是唯一一个能在移动平台上设计仿真的EDA工具。它不依赖于任何芯片,在仿真后自动生成Verilog代码,可以与其他EDA工具无缝衔接。Robei以易用(Easy to use)和易重用(Easy to reuse)为基础,是一款为芯片设计工程师量身定做的专用工具。

Robei is a cross platform chip design tool that aims to simplify design procedure, transparent intellectual properties and reduce complexity. It makes chip design like playing with boxes by breaking down hardware into three basic elements: module, port and wire. Through these elements, engineer can implement either top-down or bottom-up design. Standard Verilog code can be integrated with other EDA tools generated from design diagram. Robei also runs on embedded platforms, which makes it distinctive from other EDA design software.

 

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电话:0532-80972800

地址:青岛市高新区秀园路2号清华科创慧谷D1楼

QQ群:214910751

邮箱:linying@robei.com

网址:http://robei.com

 

 

 

TEL:+86-532-80972800

Addr:Bld. D1, Xiuyuan Rd, High-Tech Zone,

Qingdao, Shandong Province, China

QQ Group:214910751

Email:linying@robei.com

Web:http://robei.com